This patent application claims priority based on a Japanese patent application, H10-295817 filed on Oct. 16, 1998, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a plastic molding seal semiconductor device, and in particular to an LOC. (Lead on Chip) type semiconductor.
2. Description of the Related Art
Plastic molding seal semiconductor devices for electronic equipment, have been widely used. These semiconductor devices are sealed with plastic to protect the semiconductor chips laid in the semiconductor devices. Recently, these semiconductor devices, especially LSIs (Large Scaled Integrated circuits) have increased in size with the enhancement of integration. For example, the storage capacity of. memory devices is increasing, and therefore the memory devices must become larger as well. This is demonstrated by 16 MB DRAM and 64 MB DRAM, for example.
On the other hand, appliances tend to be increasingly smaller in size, which requires the semiconductor devices to be smaller. To satisfy these two divergent requirement of integration, LOC (Lead On Chip) type semiconductor devices are employed, in which one end of each of a plurality of leads is arranged overlapping with the semiconductor chip.
FIG. 1A shows the inside of the semiconductor device, FIG. 1B is a cross sectional view of the semiconductor device taken along the line Axe2x80x94A of FIG. 1A, and FIG. 1C shows a cross sectional view of the semiconductor device taken along the line Bxe2x80x94B of FIG. 1A. As shown in FIG. 1A, since this semiconductor device is of the LOC type, a plurality of leads 92 are arranged directly on the semiconductor chip 91 via a plurality of insulating tapes 93. Also mounted on the semiconductor chip 91 are a plurality of pads 95. Each pad 95 serves as an electrode used for connecting one of a plurality of terminals of the semiconductor chip 91 to an external circuit (not shown), wherein each pad 95 for a terminal is connected to a corresponding lead 92 using a bonding wire 96. The semiconductor chip 91 and most of each lead 92 are molded with a plastic sealing layer 97, that is to say, a package. The other end of each lead 92, that is to say, the end that is not molded with the plastic sealing layer 97, protrudes from the plastic sealing layer 97, and is connectable to the above-mentioned external circuit.
In the LOC semiconductor devices, the leads 92 are arranged on the semiconductor chip 91 without using a die-pad for supporting the semiconductor chip 91. Accordingly, the LOC semiconductor devices are reduced in size compared with other semiconductor devices. In other words, the LOC semiconductor device can accommodate a semiconductor chip whose size is almost 90% of the LOC semiconductor device.
In the LOC semiconductor devices, in particular the TSOP (Thin Small Outline Package) semiconductor device, the thickness, that is, the distance between the top of the upper portion 97A of the plastic sealing layer 97 and the bottom of the protruding end of the lead 92, is required to be less than 1.27 mm. Therefore, it is necessary to reduce the thickness of the plastic sealing layer 97. On the other hand, in these devices it is also required that the upper portion 97A be thick enough to cover the bonding wire 96. Consequently, both the length D1 of the upper portion 97A and the length D2 of the lower portion 97B of the plastic sealing layer 97 are designed to be thin, and in addition the length D1 is designed to be larger than the length D2, as shown in FIG. 1B.
The semiconductor chip 91 has a small linear expansivity or shrinkage ratio. On the contrary, the plastic sealing layer 97 has a large linear expansivity or shrinkage ratio. The upper portion 97A is larger in thickness than the lower portion 97B, so that the upper portion 97A shrinks more than the lower portion 97B. As a result, the plastic sealing layer 97 becomes warped while the semiconductor chip 91 remains flat. This yields a stress around the center of the semiconductor chip 91, thus causing a crack or fracture 98 in the lateral direction of the semiconductor chip 91 in the bottom side of the semiconductor chip 91 as shown in FIG. 1C.
On the other hand, the semiconductor chip 91 and the lower portion 97B could become exfoliated during the operation of the semiconductor equipment due to the difference in linear expansivity between the semiconductor chip 91 and the plastic sealing layer 97. A partial exfoliation does not cause damage to the semiconductor chip 91. However, a total exfoliation might yield a crack in the semiconductor chip 91 or in the plastic sealing layer 97. If water is absorbed in the semiconductor device, the water will vaporize to yield a crack therein.
As discussed above, the conventional LOC semiconductor device has such drawbacks that cracks may occur in the semiconductor chip or in the plastic sealing layer.
Therefore, it is an object of the present invention to provide a semiconductor device which overcomes the drawbacks in the related art. This object is achieved by the combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor chip including a top side and a bottom side; a package including an upper portion provided on the top side of the semiconductor chip and a lower portion provided on the bottom side thereof, the upper portion being thicker than the lower portion; and a resisting member provided on the bottom side of the semiconductor chip, for preventing the semiconductor chip from being bent.
According to another aspect of the present invention, there is provided a semiconductor device, wherein a plurality of grooves are formed on the bottom side of the semiconductor chip, and the resisting member is defined by the material of the package which lies in the plurality of grooves. The plurality of grooves are preferably arranged in parallel with each other in the longitudinal direction of the semiconductor chip.
According to still, another aspect of the present invention, there is provided a semiconductor device, wherein the bottom side of the semiconductor chip is convex.
According to still another aspect of the present invention, there is provided a semiconductor device, wherein the resisting member has an adhesive which makes the bottom side of the semiconductor chip adhere to the lower portion of the package. This adhesive preferably includes polyimide resin. The adhesive is preferably provided either on all of the bottom side of the semiconductor chip or on a part of the bottom side of the semiconductor chip. If the adhesive is provided on a part of the bottom of the semiconductor chip, then the adhesive is preferably provided either symmetrically in the longitudinal direction of the semiconductor chip, symmetrically in the lateral direction of the semiconductor chip, or on a plurality of separate areas of the bottom side of the semiconductor chip. The plurality of separate areas are preferably either in parallel with each other in the longitudinal direction of the semiconductor chip, or in parallel with each other in the lateral direction of the semiconductor chip. The adhesive preferably includes a polyimide tape, or a polyimide pad, which is made to adhere to the bottom side of the semiconductor chip with a metallic paste. The adhesive preferably lies along the center of the longitudinal axis of the semiconductor chip.
According to still another aspect of the present invention, there is provided a semiconductor device having a plurality of leads formed on a semiconductor chip comprising: a semiconductor chip including a top, side and a bottom side; a package including an upper portion provided on the top side of the semiconductor chip and a lower portion provided on the bottom side thereof, the upper portion being thicker than the lower portion; and a resisting member provided on the bottom side of the semiconductor chip, for preventing the semiconductor chip from being bent.
According to still another aspect of the present invention, there is provided a semiconductor device, the thickness of which is below a given value regulated by a specification of Thin Small Outline Package, comprising: a semiconductor chip including atop side and a bottom side; a package including an upper portion provided on the top side of the semiconductor chip and a lower portion provided on the bottom side thereof, the upper portion being thicker than the lower portion; and a resisting member provided on the bottom side of the semiconductor chip, for preventing the semiconductor chip from being bent.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a semiconductor chip and a package sealing the semiconductor chip, the semiconductor chip having a top side and a bottom side, and a plurality of leads being arranged on the top side of the semiconductor chip, the method comprising: forming a resisting member on the bottom side of the semiconductor chip, for preventing the semiconductor chip from being bent.
According to still another aspect of the present invention, there is provided a semiconductor device, having a thickness below a given value regulated by a specification of Thin Small Outline Packages, comprising: a semiconductor chip including a top side and a bottom side; a package including an upper portion provided on said top side of the semiconductor chip and a lower portion provided on said bottom side thereof, said upper portion being thicker than said lower portion; and a resisting member provided on said bottom side of said semiconductor chip, for preventing said semiconductor chip from being bent.
This summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.